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Sr ASIC/FPGA VHDL Design Engineer with SECRET clearance
Camden, NJ · $115,000 to $140,000OPEN JOB: Sr ASIC/FPGA VHDL Design Engineer with SECRET clearance
LOCATION: Camden, New Jersey (outside of Philadelphia)
****Relocation Assistance Available
SCHEDULE: 9/80 (every other Friday off) schedule
SALARY: $115,000 to $140,000
FULL-TIME
BENEFITS - Full
INDUSTRY: Aerospace / Defense
Job Description:
Essential Functions:
Qualifications:
Preferred Additional Skills:
A big plus if the candidate possesses “any” of the following:
If you are interested in pursuing this opportunity, please respond back and include the following:
Upon receipt, one of our managers will contact you to discuss the position in full detail.
JASON DENMARK
Recruiting Manager
INTERMEDIA GROUP, INC.
EMAIL: jdenmark@intermediagroup.com
LINKEDIN: https://www.linkedin.com/in/jasondenmark
VISIT OUR FULL LIST OF OPEN POSITIONS:
https://intermediagroup.catsone.com/careers
LOCATION: Camden, New Jersey (outside of Philadelphia)
****Relocation Assistance Available
SCHEDULE: 9/80 (every other Friday off) schedule
SALARY: $115,000 to $140,000
FULL-TIME
BENEFITS - Full
INDUSTRY: Aerospace / Defense
Job Description:
- Schedule: 9/80 Regular with every other Friday off
- Reporting to the Manager, Engineering (ASIC/FPGA), the Senior Member of Engineering Staff (SMES) will be part of the key ASIC/FPGA design team, responsible for the delivery of FPGA/ASICs for high-speed crypto applications. S/he will architect, implement high speed crypto architectures, on ASICs/Xilinx Zynq/MPSOC class FPGAs, with hands on design/debug with Ethernet, TCP/IP protocols.
- The company has state-of-the-art EDA flows/methodologies including Synopsys DC/Primetime/Synplify, Xilinx/Intel/Microchip EDA with HLS, Mentor EDA Family suite: Questa, VIPs, UVM framework, Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), Questa Lint, and Catapult (HLS).
- This is a key, high impact role in the organization to ensure robust quality and delivery of communication products for National Security.
Essential Functions:
- Responsible for deriving engineering specifications from system requirements and developing detailed architecture
- Execute design (RTL AND/OR HLS (C++ to RTL)) and RTL quality (RDC, CDC, Formal, Lint)
- Generate test plans
- Perform module level verification, synthesis/STA, Lab debug, SW driven validation on Linux based SOC evaluation boards
- Silicon/FPGA bring up, characterization and production ramp/support/collateral
Qualifications:
- Active SECRET Clearance
- BSEE.
- 5+ year’s equivalent experience developing, implementing, and verification of high-performance communications/networking ASIC/FPGA products.
- Experience mapping algorithms and standards (Ethernet, TCP/IP, AXI) to hardware and architecture/system design tradeoffs.
- Proficient with CDC, RDC. Formal EDA.
- Proficient in VHDL is a must
- Proficient with Synthesis/PAR: SDC, Synopsys Synplify, Vivado
- Strong logic/board debug, and analytical skills.
- Experience with project leadership and EVM
- Excellent written, verbal, and presentation skills.
Preferred Additional Skills:
A big plus if the candidate possesses “any” of the following:
- Proficiency in C++ (OOP)
- Proficiency with Xilinx MPSOC design with writing/debugging with SDKs, BSPs on bare metal/PetaLinux OS.
- Knowledge of PCIe, NVMe, USB protocols.
- Experience with High level synthesis (Xilinx Vivado HLS, AND/OR Mentor Calypto).
If you are interested in pursuing this opportunity, please respond back and include the following:
- MS WORD Resume
- required compensation.
- Contact information.
- Availability
Upon receipt, one of our managers will contact you to discuss the position in full detail.
JASON DENMARK
Recruiting Manager
INTERMEDIA GROUP, INC.
EMAIL: jdenmark@intermediagroup.com
LINKEDIN: https://www.linkedin.com/in/jasondenmark
VISIT OUR FULL LIST OF OPEN POSITIONS:
https://intermediagroup.catsone.com/careers